Pop-up Image

Mr.Sateesh Kourav
APID: 7617
capJUNIOR RESEARCH FELLOWSHIP (JRF) at Indian Institute of Information Technology, Design & Manufacturing, Jabalpur JABALPUR, MADHYA PRADESH
Please login
 

Home / APID Profiles

My Biography

As a Junior Research Fellow in the Department of More Electronics and Communication Engineering, I contributed to research projects focused on embedded systems and VLSI design. Master of Technology (M.Tech) in Embedded System & VLSI Design Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2022] Specialized in Embedded Systems and VLSI Design, with a focus on digital electronics, hardware-software integration, and advanced circuit design. Bachelor of Engineering (B.E.) Electronics and Communication Engineering] Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2019] Completed foundational studies in engineering, gaining a broad understanding of electronics, digital systems, and related technologies. Publications: I have published 14 research articles in prestigious national and international journals, demonstrating my expertise and contributions to the field of Embedded Systems and VLSI Design.
Hardware-Software Integration: Skilled in integrating hardware and software components to create efficient and reliable embedded systems.
Programming Languages: Proficient in Verilog and VHDL for hardware description and system design.
Design Tools: Experienced with a variety of design tools, including Diptrace, Origin, Layout Editor, Draw.io, Microsoft Visio, Symicade, and Cadence.

Area Of Expertise

Electronics

Area of Intrest

FPGA

Honors and Awards

User has not updated his/her Awards & Honors.

Career Timeline

Academic Identity

User not updated academic id.

Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects
User has not updated his/her Conferences.

Feed

Imam Prayogo Pujiono

hello, I’m looking for friends to collaborate on writing articles in the field of informatics / Read More computers, if you are interested or want to ask, please send a message to me at [email protected]

#Apid #Academic #researchers #scholars #academicians #students

EGOP, Samuel Ezekiel

Hello guys, I am a researcher and lecturer in the department of Civil Engineering at the Rivers Read More State University.

#Apid #Academic #researchers #scholars #academicians #students

Sonia Kamoun

Hello every one

#Apid #Academic #researchers #scholars #academicians #students

Salanmi Chyrmang

Hello

#Apid #Academic #researchers #scholars #academicians #students

Gizachew Diga

The is the best ecosystem for communication with global scientific community.

#Apid #Academic #researchers #scholars #academicians #students

Rajasekhar Reddy Poonuru

Pharmaceutics formulation people

Like: 0

#Apid #Academic #researchers #scholars #academicians #students

Biswanath Mudi

Hi everyone, our recent filed studio at dharampur, Gujarat , completed by the students of Institute Read More of Architecture and Planning | Nirma University

#Apid #Academic #researchers #scholars #academicians #students

Yenealem Gemi Mekuria

Hello

#Apid #Academic #researchers #scholars #academicians #students

Satish Kumar

Happy New Year, APIDians!

#Apid #Academic #researchers #scholars #academicians #students

Amit Rai

Happy New Year APID’ans

#Apid #Academic #researchers #scholars #academicians #students

User has not Posted Anything.

Publications

Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects

User has not updated his/her Conferences.

Editorial Roles
Electronics & Telecommunication Engineering

No Reviewing details added by the User