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Mr.Sateesh Kourav
APID: 7617
capJUNIOR RESEARCH FELLOWSHIP (JRF) at Indian Institute of Information Technology, Design & Manufacturing, Jabalpur JABALPUR, MADHYA PRADESH
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My Biography

As a Junior Research Fellow in the Department of More Electronics and Communication Engineering, I contributed to research projects focused on embedded systems and VLSI design. Master of Technology (M.Tech) in Embedded System & VLSI Design Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2022] Specialized in Embedded Systems and VLSI Design, with a focus on digital electronics, hardware-software integration, and advanced circuit design. Bachelor of Engineering (B.E.) Electronics and Communication Engineering] Gyan Ganga Institute of Technology & Sciences (G.G.I.T.S), affiliated with Rajiv Gandhi Proudyogiki Vishwavidyalaya (R.G.P.V.), Bhopal [Year of 2019] Completed foundational studies in engineering, gaining a broad understanding of electronics, digital systems, and related technologies. Publications: I have published 14 research articles in prestigious national and international journals, demonstrating my expertise and contributions to the field of Embedded Systems and VLSI Design.
Hardware-Software Integration: Skilled in integrating hardware and software components to create efficient and reliable embedded systems.
Programming Languages: Proficient in Verilog and VHDL for hardware description and system design.
Design Tools: Experienced with a variety of design tools, including Diptrace, Origin, Layout Editor, Draw.io, Microsoft Visio, Symicade, and Cadence.

Area Of Expertise

Electronics

Area of Intrest

FPGA

Honors and Awards

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Career Timeline

Academic Identity

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Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects
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Aishwarya Jain

Ms Aishwarya Jain is currently working as an Assistant Professor at Sinhgad College of Pharmacy, Read More Vadgaon (Bk), Pune. She has half a decade of experience in Academics. Her research work has been recognized with awards and accolades at national and international levels. Her academic achievements are she has won more than 50 plus awards such as RECIPIENT of “BHARAT SHIKSHA GAURAV PURASKAR” with “CERTIFICATE OF EDUCATION EXCELLENCE”, WINNER AS BEST PAPER at National level ANVESHAK 2022, WOMEN EMPOWERMENT AWARD at Bharti Vidyapeeth’s Poona College of Pharmacy, Pune. She has published several papers in reputable journals, Aishwarya’s dedication to education, research, and personal growth has been reflected in her involvement as an editorial member and reviewer for various journals and publication houses. With her passion for innovation, interdisciplinary collaboration, and a strong academic foundation, She continues to make significant contributions to the field of pharmaceutical education and research. Her determination, adaptability, and broad skill set make her a valuable asset in any professional setting.
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Suja Kumari S

Passionate in teaching, counseling and research…Always like to do something different and worthy Read More .. Interested in inno
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Jatinder Kaur

i am dedicated researcher in the direction of sustainable development and has worked over 10 years Read More in this regard.
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Vivek Verma

hello to all

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Mostafa Hussien

Studying biological applications of metal complexes and organometallic comp. and interested in Read More Bioinformatic and drug design.
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SUNITHA P S

HELLO
EVIDENCE BASED PRACTICE IS VERY IMPORTANT FOR ACADEMIC EXALLENCE

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SUNITHA P S

HELLO,

EVIDENCE BASED PRACTICE IS VERY IMPORTENT FOR ACEDEMIC EXALLENCE

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Dr. Bakhat Ali

hello

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Dr. Bakhat Ali

I have interest to teach general chemistry and similarly interest to work in multidirectional Read More research work
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Aditi Mantri

Hello to the researchers

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Publications

Project: An ASIC design of Area and Speed Efficient Floating-Point Arithmetic and Logical Unit Implementation on Hybrid FPGAs
Goal: Area and Speed Efficient ALU
Current Stage: completed
Starting Date: 13/05/2020
Sponsored by: GGITS
Projects

User has not updated his/her Conferences.

Editorial Roles
Electronics & Telecommunication Engineering

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